Semiconductor package and method for producing same

ABSTRACT

An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a semiconductor package and a methodfor producing the same. In particular, the present invention relates toa semiconductor package having a Panel Level Package (hereinafterreferred to as PLP) structure involving a thin-film wiring step and anassembly step in a large panel scale, and relates to a method forproducing the same.

2. Description of the Related Art

With a recent demand for highly functional, compact electronicequipment, high density integration and, moreover, high-densitypackaging of electronic parts have made progress. Accordingly, asemiconductor device used in such electronic equipment has been reducedin size to a greater degree than ever before.

Japanese Patent Publication No. 2010-219489 describes an example of amethod for producing a semiconductor package aiming at increasing thedensity of electronic parts and enhancing compactness thereof.

The basic structure of the semiconductor device described in JapanesePatent Publication No. 2010-219489 is shown in FIG. 4, and thesemiconductor device is described below.

A semiconductor device 20 includes a support plate 1 formed of a curedresin or a metal. A semiconductor chip 2 is disposed on one main face ofthe support plate 1 such that an element circuit surface (front sidesurface) of the semiconductor chip 2 faces upward, and the surface (backside surface) opposite to the element circuit surface is fixed on thesupport plate 1 with an adhesive 3. An insulating material layer 4 isformed singly on the entire main face of the support plate 1, coveringthe element circuit surface of the semiconductor chip 2. Wiring layers 5comprising a conductive metal such as copper are formed on this singleinsulating material layer 4 and are partially extended to peripheralregions of the semiconductor chip 2. A conductive part (via part) 6 thatelectrically connects an electrode pad of the semiconductor chip 2 andthe wiring layers 5 is formed in the insulating material layer 4 formedon the element circuit surface of the semiconductor chip 2. Thisconductive part 6 and the wiring layers 5 are collectively formed andare integrated. A plurality of solder balls 7 that are externalelectrodes are formed on predetermined positions of the wiring layers 5.Wiring protection layers (solder resist layers) 8 are further formed onthe insulating material layer 4 and the wiring layers 5 excluding partsjoined to the solder balls 7.

A method for producing a conventional PLP is described with reference toFIGS. 5A to 5C.

FIGS. 5A to 5C show an overview of a method for producing a package, inwhich a single package includes three semiconductor chips 2. Note thatFIGS. 5A to C only show one package, while in actual practice aplurality of packages are assembled simultaneously on a large panel.

The method for producing a package includes steps (A), (B), and (C).

(A) A Step of Mounting Semiconductor Chips (See FIG. 5A)

Semiconductor chips 2 are fixed, with an adhesive, on one main face of asupport plate 1 formed of a cured resin, stainless steel, or a metalsuch as a 42 alloy, with the element circuit surface facing upward.

(B) A Step of Encapsulating (See FIG. 5B)

The face of the support plate 1, on which the semiconductor chips 2 aremounted, is encapsulated with an insulating material layer 4.

(C) A Step of Forming Wiring Layers (See FIG. 5C)

Wiring layers 5 via-connected to electrodes of the semiconductor chips2, through via conductors 6, are formed.

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

In the conventional PLP shown in FIG. 4, a final product includes asupport plate 1. Thus, an increase in mounting rate of semiconductorchips 2 results in warping of a panel during production and interferenceof the semiconductor chips 2 with a device for producing an PLP.

An increase in thicknesses of the semiconductor chips 2 and a decreasein distance between the adjacent semiconductor chips 2 result in aninsulating resin being unable to enter a space therebetween. If thethickness of a resin material is increased to solve this problem, thethickness of the semiconductor package itself cannot be reduced.

An increase in thicknesses of the semiconductor chips causes an increasein distance between the support plate 1 and each wiring layer 5. Thus,it becomes difficult to perform boring of a via by laser and connectionby copper plating for connecting the support plate 1 and each wiringlayer 5.

An object of the present invention is to provide a semiconductor packagewith which it is possible to reduce a volume of an encapsulation resinand to easily embed a resin regardless of thicknesses of semiconductorchips and a small distance between adjacent semiconductor chips, as wellas to provide a thin semiconductor package with which a final productincludes no support flat plate.

The inventors of the present invention found that these problems can besolved by a structure in which semiconductor chips are embedded in therespective cavity parts formed by copper plating and completed thepresent invention.

That is, the present invention relates to a semiconductor package and amethod for producing the same as described below.

(1) A semiconductor package having a structure wherein semiconductorchips are accommodated in cavity parts of a support which is formed bycopper plating and includes the cavity parts.

(2) The semiconductor package according to the item (1) above, whereineach cavity part has a height lower than each semiconductor chip toavoid interference between a semiconductor chip arrangement jig andcavity walls that form the cavity parts.

(3) The semiconductor package according to the item (1) above, whereineach cavity wall that is an outer peripheral part of the semiconductorpackage includes a step extended toward an upper part, and the step hasa height lower than each semiconductor chip to avoid interferencebetween the semiconductor chip arrangement jig and the cavity walls.

(4) A semiconductor package including:

a support;

semiconductor chips arranged on one surface of the support via anadhesive layer, with element circuit surfaces of the semiconductor chipsfacing upward;

an insulating material layer that encapsulates the semiconductor chipsand the periphery thereof;

in the insulating material layer, openings formed on electrodes that areplaced on the element circuit surfaces of the semiconductor chips;

conductive parts formed in the openings to connect with the electrodesof the semiconductor chips;

wiring layers formed on the insulating material layer to connect withthe conductive parts and partially extended to peripheral regions of thesemiconductor chips; and

external electrodes formed on the wiring layers, wherein

the support is formed by a copper plated object having cavity parts thataccept the semiconductor chips on the one surface, the semiconductorchips being accommodated in the respective cavity parts, and

the insulating material layer is on the other surface of the support.

(5) A method for producing a semiconductor package, including, in thefollowing order, the steps of:

laying a copper foil on one main face of a support flat plate;

performing electroplating to form a copper plating layer on the copperfoil;

performing electroplating to form cavity parts on the copper platinglayer;

fixing surfaces opposite to element circuit surfaces of thesemiconductor chips in the cavity parts with an adhesive;

resin-encapsulating the semiconductor chips with an insulating resin toform an encapsulation resin layer;

forming openings in the insulating material layer upon positionscorresponding to electrodes arranged on the element circuit surfaces ofthe semiconductor chips;

forming, on the insulating material layer, wiring layers partiallyextended to peripheral regions of the semiconductor chips, and forming,in the openings of the insulating material layer, conductive partsconnected to the electrodes of the semiconductor chips;

forming a solder resist on the wiring layer except in portionscorresponding to the openings;

forming external electrodes on parts of the wiring layer correspondingto the openings;

separating the support flat plate from the copper foil; and

forming an insulating material layer on the copper foil afterseparation.

(6) A method for producing a semiconductor package having a support flatplate, including, in the following order, the steps of:

laying a copper foil on one main face of the support flat plate;

performing electroplating to form a copper plating layer on the copperfoil;

performing electroplating to form cavity parts on the copper platinglayer;

fixing surfaces opposite to element circuit surfaces of thesemiconductor chips in the cavity parts with an adhesive;

resin-encapsulating the semiconductor chips with an insulating resin toform an encapsulation resin layer;

forming openings in the insulating material layer upon positionscorresponding to electrodes arranged on the element circuit surfaces ofthe semiconductor chips;

forming, on the insulating material layer, wiring layers partiallyextended to peripheral regions of the semiconductor chips, and forming,in the openings of the insulating material layer, conductive partsconnected to the electrodes of the semiconductor chips;

forming a solder resist on the wiring layer except in portionscorresponding to the openings; and

forming external electrodes on parts of the wiring layer correspondingto the openings.

(7) The method for producing a semiconductor package according to theitem (5) or (6) above, wherein

the cavity parts are formed by forming parts that are not copper-platedby pattern plating using a resist.

(8) A method for producing a semiconductor package, including, in thefollowing order, the steps of:

laying a copper foil on each of both surfaces of a support flat plate;

performing electroplating to form a copper plating layer on the copperfoil;

performing electroplating to form cavity parts on the copper platinglayer;

fixing surfaces opposite to element circuit surfaces of thesemiconductor chips in the cavity parts with an adhesive;

resin-encapsulating the semiconductor chips with an insulating resin toform an encapsulation resin layer;

forming openings in the insulating material layer upon positionscorresponding to electrodes arranged on the element circuit surfaces ofthe semiconductor chips;

forming, on the insulating material layer, wiring layers partiallyextended to peripheral regions of the semiconductor chips, and forming,in the openings of the insulating material layer, conductive partsconnected to the electrodes of the semiconductor chips;

forming a solder resist on the wiring layer except in portionscorresponding to the openings;

forming external electrodes on parts of the wiring layer correspondingto the openings

to form package parts on both surfaces of the support flat plate;

separating the support flat plate from the copper foils of the packageparts to obtain two package parts; and

forming an insulating material layer on the copper foils of the twopackage parts.

Advantageous Effects of Invention

Advantageous effects of the semiconductor package of the presentinvention include the following.

-   -   Cavity parts of a support that is formed by copper plating        accommodate the respective semiconductor chips; as a result, a        volume to be encapsulated using an encapsulation resin is made        smaller, and the resin can be easily embedded regardless of        thicknesses of semiconductor chips and a small distance between        adjacent semiconductor chips.    -   A final product has a structure supported by a support formed by        copper plating, thus ground connection with the support formed        by copper plating is established through an ordinary via for        interlayer connection, and the EMI shielding effect can be        improved.    -   A final product of the semiconductor package can be configured        to include no support flat plate. The semiconductor package thus        can be thin and can be applied to a wide range of products such        as mobile products.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are drawings showing the steps of forming a support thatis formed by copper plating, including cavity parts on a support flatplate.

FIGS. 1E to 1H are drawings showing the steps of arranging semiconductorchips in the respective cavity parts of a support that is formed bycopper plating, forming an encapsulation resin layer, and forming awiring layer on the surface of the encapsulation resin layer.

FIGS. 1I to 1L are drawings showing steps of forming a solder resistthat has openings on the surface of a wiring layer, forming externalelectrodes in the openings of the solder resist, separating between asupport flat plate and a semiconductor package, and forming aninsulating layer on the back surface of the separated semiconductorpackage.

FIG. 2A is a drawing showing a state where semiconductor package partsare formed on both surfaces of a support flat plate, FIG. 2B is adrawing showing a state where the support flat plate is separated fromthe semiconductor package parts, and FIG. 2C is a drawing showing astate where insulating material layers are formed on one surfaces ofsemiconductor package parts.

FIG. 3 is a partially enlarged view of one of the semiconductorpackaging parts shown in FIG. 2A.

FIG. 4 is a drawing of a structure of a conventional PLP.

FIG. 5A to 5C are drawings showing an overview of the steps of producinga conventional PLP.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are described below. Although thefollowing description is made with reference to the drawings, thesedrawings are merely for the sake of illustration, and the presentinvention is by no means limited thereto.

The semiconductor package of the present invention has a structure inwhich semiconductor chips are accommodated in cavity parts of a supportwhich is formed by copper plating and includes the cavity parts.

Embodiments of the semiconductor package having the structure aredescribed below in detail with reference to the drawings.

First Embodiment

The present embodiment is described with reference to FIGS. 1-1, 1-2,and 1-3.

FIG. 1A is a drawing of a support flat plate 1. The support flat plate 1is a flat plate having a uniform thickness, and as the support flatplate 1, a cured resin obtained by curing an insulating resin or a metalhaving high rigidity such as SUS or a 42 alloy can be used. The supportflat plate 1 imparts rigidity to a panel and serves to prevent warpingin production steps. The support flat plate 1 is thus only required tohave a thickness with which warping does not occur.

The support flat plate 1 remaining in a final product not only functionsas a stiffener, a heat radiation plate, an electromagnetic shield, butalso serves as a carrier for transferring a product in the productionsteps. Stainless steel is thus preferably used as the support flat plate1 for the ease of handling of a panel, prevention of warping, and theease of dividing.

FIG. 1B is a drawing showing a state where a copper foil 6 is laid onthe support flat plate 1 via an adhesive layer 5.

As shown in an enlarged view of a part X of FIG. 1B, the copper foil 6is an ordinary copper foil with a carrier and has a two-layer structureof an ultrathin copper foil 6 a and a copper foil carrier 6 b.

The front and rear of the carrier surface can be changed during layingin accordance with usage, and when the support flat plate 1 is to beincluded in a final product, the copper foil carrier may be removed inthis step.

The case where the support flat plate 1 is eventually removed from aproduct is described below.

FIG. 1C is a drawing showing a state where a copper plating layer 7 isformed on the copper foil 6 by electrolytic copper plating to have anin-plane uniform thickness. The copper plating layer 7 is to be asurface on which semiconductor chips 9 are placed.

FIG. 1D is a drawing showing a state where cavity walls 8 a are formedon the copper plating layer 7 using a process of forming wiring byordinary electroplating to form a support 2 by copper plating. Eachcavity part 8 of the support 2 that is formed by copper plating isformed of the cavity walls 8 a that are formed by copper plating and acavity bottom surface 8 b that is a surface of the copper plating layer7.

The process of forming wiring by ordinary electroplating is, forexample, a process of laminating a photosensitive dry film resist on thecopper plating layer 7, subjecting the photosensitive dry film resist toexposure to light and developing to perform patterning, forming, byelectroplating, the cavity walls 8 a that are formed by copper platingin an opening that is formed by the patterning, and removing the resist.

The cavity part 8 preferably has a height lower than the semiconductorchips 9. In the present invention, the height of the cavity part 8 isreferred to as the height of the cavity.

FIG. 1E is a drawing showing a state where the semiconductor chips 9 arearranged in the respective cavity parts 8.

The semiconductor chips 9 are arranged by applying an adhesive to theback surfaces of the semiconductor chips 9 or the cavity bottom surfacesof the cavity parts 8, picking the semiconductor chips 9 up and fixingthem on the cavity bottom surfaces 8 b by a die-bonding device. At thattime, when the heights of the cavity parts 8 are higher than thesemiconductor chips 9, a semiconductor chip arrangement jig (e.g.,collet) may be in contact with the cavity walls 8 a. Each cavity part 8thus preferably has a height equal to or lower than the semiconductorchips 9.

FIG. 1F is a drawing showing a state where an encapsulation resin layer10 formed of an insulating resin that encapsulates the semiconductorchips 9 is formed.

For example, lamination, transfer molding, or compression molding can beused for the encapsulation.

FIG. 1G is a drawing showing a state where a copper foil 11 is laid onthe encapsulation resin layer 10.

The copper foil 11 is provided to form a wiring layer on the surface ofthe encapsulation resin layer 10. Meanwhile, as a substitute forproviding the copper foil 11, a seed layer may be formed on the surfaceof the encapsulation resin layer 10 by, for example, electrolessplating, sputtering, or PVD, and a copper plating film is then formed byelectroplating.

FIG. 1H is a drawing showing a state where a wiring layer 12 is formedon the surface of the encapsulation resin layer 10.

This wiring layer 12 can be formed by, for example, subjecting thecopper foil 11 to a pretreatment such as blackening or etching ifnecessary, thereafter subjecting the copper foil 11 to, for example, atreatment for forming an opening by laser or a desmear treatment, andthen subjecting to a process of forming wiring by ordinaryelectroplating.

FIG. 1I is a drawing showing a state where a solder resist 13 is formedon the wiring layer 12.

Only wiring parts that are required to be soldered are caused to beexposed by forming openings 15, and parts that are not require to besoldered are coated with an insulating material such as a thermosettingepoxy resin to form a solder resist 13.

FIG. 1J is a drawing showing a state where solder balls 17 that areexternal electrodes are formed in the openings 15.

FIG. 1K is a drawing showing a state where a package part 20 and asupport flat plate part 21 are separated from each other.

The semiconductor package according to the present embodiment as a finalproduct has a structure of including no support flat plate. The packagepart 20 and the support flat plate part 21 are thus separated from eachother. Specifically, incisions are made in edges of the material of thecopper foil 6 from both ends of the solder resist 13 to separate betweenthe ultrathin copper foil 6 a and the copper foil carrier 6 b.

The incisions are made by cutting the inside of the size of the materialof the copper foil, considering cutting equipment and the accuracy ofattaching the copper foil.

FIG. 1L is a drawing showing a state where a solder resist or aninsulating material layer 14 is formed on the ultrathin copper foil 6 aadhered to the copper plating layer 7 side of the package part 20separated from the support flat plate part 21.

A semiconductor package 30 can be obtained by performing a surfacetreatment such as gold plating on the wiring layer 12 in the openings 15and dividing, if necessary.

When the copper foil carrier 6 b is removed in the step shown in FIG.1B, that is, a final product including a support flat plate 1 isproduced, a semiconductor package including a support flat plate can beobtained by performing a surface treatment such as gold plating on partsof the wiring layer 12 exposed by the openings 15 in an object in thestate where a solder resist 13 is formed shown in FIG. 1I and dividing.

Second Embodiment

The present embodiment is described with reference to FIGS. 2A to 2C.The present embodiment is an application example of the firstembodiment.

In the present embodiment, a copper foil 6 is laid via a resin 5 on eachof the both surfaces of the support flat plate 1 in the object shown inFIG. 1B according to the first embodiment to obtain a support flat platepart 21.

FIG. 2A is a drawing showing a state where both surfaces of the supportflat plate 1 is subjected to the same step as performed in the firstembodiment to form package parts 20 and 20′ on both surfaces of thesupport flat plate part 21.

The formation of the package parts 20 and 20′ on both surfaces of thesupport flat plate part 21 requires a step of arranging and fixing thesemiconductor chips 9 in the respective cavity parts 8 on one surface(front side surface) of the support flat plate part 21, and thenarranging other semiconductor chips 9 in the respective cavity parts 8on the other surface (back side surface) of the support flat plate part21.

In this case, as described in the first embodiment, formation of cavityparts 16 having cavity walls 8 a that have lower heights than thesemiconductor chips 9 results in contact of the surfaces of thesemiconductor chips 9 arranged on the front side surface in advance witha device table in the arrangement of the semiconductor chips 9 on theback side surface. This causes a reduction in a yield.

The cavities 16 having heights equal to or higher than the semiconductorchips 9 are thus formed in the present embodiment.

FIG. 3 is an enlarged view of a cavity part 16 in a package part shownin FIG. 2A.

Each cavity wall of each cavity part 16 has a step 17, and each cavitypart 16 has a two-step structure of a cavity 16 a having a smaller widthand a cavity 16 b having a larger width.

The heights of the cavity 16 a are required to be heights with which ajig does not interfere with the cavity walls of the cavities 16 b in thearrangement of the semiconductor chips. The sizes of the openings in thecavities 16 b are required to be sizes with which a jig does notinterfere with the cavity walls of the cavities 16 b in the arrangementof the semiconductor chips.

Such cavity parts each having a two-step structure can be employed asthe cavity parts in the first embodiment.

FIG. 2B is a drawing showing a state where the package parts 20 and 20′are separated from the support flat plate part 21.

FIG. 2C is a drawing showing a state where a solder resist or aninsulating material layer 14 is formed on each ultrathin copper foil 6 aadhered to each copper plating layer 7 of each of the package parts 20and 20′ separated from the support flat plate part 21.

Subsequently, a surface treatment such as gold plating is performed onparts of each wiring layer 12 in the openings 15 if necessary, anddividing is performed, to obtain semiconductor packages 30 and 30′.

Advantages of the semiconductor package of the present invention are asfollows.

-   -   The final product of the semiconductor package can be configured        to include no support flat plate. The semiconductor package thus        can be thin and can be applied to a wide range of products such        as mobile products.    -   The support flat plate can be removed from the final product.        The warping of the panel in production thus can be prevented        even when the semiconductor package is thin.    -   The semiconductor chips can be embedded in the respective cavity        parts. Thus, the volume of the insulating resin to be embedded        is reduced, and the resin can be easily embedded even when the        semiconductor chips are thick, and the distance between adjacent        semiconductor chips are small. Moreover, the variations in        thickness of the resin on the semiconductor chips can be        reduced, and electrical characteristics such as pass        characteristics and characteristic impedance are excellent.    -   The cavity parts are formed by copper plating. Thus, unlike the        etching, the accuracy of dimension in the depth direction is        excellent.    -   A copper plated object is used as a support in the final        product, thus ground connection is established with the        copper-plated support plate through an ordinary via for        interlayer connection, and the EMI shielding effect can be        improved.

With a structure of having cavities, a distance between a support formedby copper plating and a wiring layer can be reduced even when thesemiconductor chips are thick, facilitating laser boring of a via andconnection by copper plating.

1. A semiconductor package having a structure wherein semiconductorchips are accommodated in cavity parts of a support which is formed bycopper plating and includes the cavity parts.
 2. The semiconductorpackage according to claim 1, wherein each cavity part has a heightlower than each semiconductor chip to avoid interference between asemiconductor chip arrangement jig and cavity walls that form the cavityparts.
 3. The semiconductor package according to claim 1, wherein eachcavity wall that is an outer peripheral part of the semiconductorpackage includes a step extended toward an upper part, and the step hasa height lower than each semiconductor chip to avoid interferencebetween the semiconductor chip arrangement jig and the cavity walls. 4.A semiconductor package including: a support; semiconductor chipsarranged on one surface of the support via an adhesive layer, withelement circuit surfaces of the semiconductor chips facing upward; aninsulating material layer that encapsulates the semiconductor chips andthe periphery thereof; in the insulating material layer, openings formedon electrodes that are placed on the element circuit surfaces of thesemiconductor chips; conductive parts formed in the openings to connectwith the electrodes of the semiconductor chips; wiring layers formed onthe insulating material layer to connect with the conductive parts andpartially extended to peripheral regions of the semiconductor chips; andexternal electrodes formed on the wiring layers, wherein the support isformed by a copper plated object having cavity parts that accept thesemiconductor chips on the one surface, the semiconductor chips beingaccommodated in the respective cavity parts, and the insulating materiallayer is on the other surface of the support.
 5. A method for producinga semiconductor package, including, in the following order, the stepsof: laying a copper foil on one main face of a support flat plate;performing electroplating to form a copper plating layer on the copperfoil; performing electroplating to form cavity parts on the copperplating layer; fixing surfaces opposite to element circuit surfaces ofthe semiconductor chips in the cavity parts with an adhesive;resin-encapsulating the semiconductor chips with an insulating resin toform an encapsulation resin layer; forming openings in the insulatingmaterial layer upon positions corresponding to electrodes arranged onthe element circuit surfaces of the semiconductor chips; forming, on theinsulating material layer, wiring layers partially extended toperipheral regions of the semiconductor chips, and forming, in theopenings of the insulating material layer, conductive parts connected tothe electrodes of the semiconductor chips; forming a solder resist onthe wiring layer except in portions corresponding to the openings;forming external electrodes on parts of the wiring layer correspondingto the openings; separating the support flat plate from the copper foil;and forming an insulating material layer on the copper foil afterseparation.
 6. A method for producing a semiconductor package having asupport flat plate, including, in the following order, the steps of:laying a copper foil on one main face of the support flat plate;performing electroplating to form a copper plating layer on the copperfoil; performing electroplating to form cavity parts on the copperplating layer; fixing surfaces opposite to element circuit surfaces ofthe semiconductor chips in the cavity parts with an adhesive;resin-encapsulating the semiconductor chips with an insulating resin toform an encapsulation resin layer; forming openings in the insulatingmaterial layer upon positions corresponding to electrodes arranged onthe element circuit surfaces of the semiconductor chips; forming, on theinsulating material layer, wiring layers partially extended toperipheral regions of the semiconductor chips, and forming, in theopenings of the insulating material layer, conductive parts connected tothe electrodes of the semiconductor chips; forming a solder resist onthe wiring layer except in portions corresponding to the openings; andforming external electrodes on parts of the wiring layer correspondingto the openings.
 7. The method for producing a semiconductor packageaccording to claim 5, wherein the cavity parts are formed by formingparts that are not copper-plated by pattern plating using a resist.
 8. Amethod for producing a semiconductor package, including, in thefollowing order, the steps of: laying a copper foil on each of bothsurfaces of a support flat plate; performing electroplating to form acopper plating layer on the copper foil; performing electroplating toform cavity parts on the copper plating layer; fixing surfaces oppositeto element circuit surfaces of the semiconductor chips in the cavityparts with an adhesive; resin-encapsulating the semiconductor chips withan insulating resin to form an encapsulation resin layer; formingopenings in the insulating material layer upon positions correspondingto electrodes arranged on the element circuit surfaces of thesemiconductor chips; forming, on the insulating material layer, wiringlayers partially extended to peripheral regions of the semiconductorchips, and forming, in the openings of the insulating material layer,conductive parts connected to the electrodes of the semiconductor chips;forming a solder resist on the wiring layer except in portionscorresponding to the openings; forming external electrodes on parts ofthe wiring layer corresponding to the openings to form package parts onboth surfaces of the support flat plate; separating the support flatplate from the copper foils of the package parts to obtain two packageparts; and forming an insulating material layer on the copper foils ofthe two package parts.